INSTR_FETCH_ERR=Val_0x0, OPERAND_INVALID=Val_0x0, DBG_INSTR=Val_0x0, UNDEF_INSTR=Val_0x0, DMAGO_ERR=Val_0x0, MGR_EVNT_ERR=Val_0x0
Fault Type DMA Manager Register
| UNDEF_INSTR | This bit indicates whether the DMA manager was attempting to execute an undefined instruction. 0 (Val_0x0): Defined instruction. 1 (Val_0x1): Undefined instruction. |
| OPERAND_INVALID | This bit indicates whether the DMA manager was attempting to execute an instruction operand that was not valid for the configuration of the DMAC. 0 (Val_0x0): Valid operand. 1 (Val_0x1): Invalid operand. |
| DMAGO_ERR | This bit indicates whether the DMA manager was attempting to execute DMAGO with inappropriate security permissions. 0 (Val_0x0): The DMA manager has appropriate security to execute DMAGO. 1 (Val_0x1): The DMA manager thread in the non-secure state attempted to execute DMAGO to create a DMA channel operating in the secure state. |
| MGR_EVNT_ERR | This bit indicates whether the DMA manager was attempting to execute DMAWFE or DMASEV with inappropriate security permissions. 0 (Val_0x0): The DMA manager has appropriate security to execute DMAWFE or DMASEV. 1 (Val_0x1): The DMA manager thread in the non-secure state attempted to execute either:
|
| INSTR_FETCH_ERR | This bit indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA manager performs an instruction fetch. 0 (Val_0x0): OKAY response. 1 (Val_0x1): EXOKAY, SLVERR, or DECERR response. |
| DBG_INSTR | If the DMA manager aborts, this bit indicates whether the erroneous instruction was read from the system memory or from the debug interface. 0 (Val_0x0): Instruction that generated an abort was read from system memory. 1 (Val_0x1): Instruction that generated an abort was read from the debug interface. |